Dr. Luca Fasoli,
Senior Vice President, Silicon Technology & Manufacturing at Western Digital
Dr. Luca Fasoli is responsible for the strategy and the development of Western Digital solid-state memory technologies. Previously, he held engineering management positions at Waferscale Integration, STMicroelectronics, Matrix Semiconductor and at SanDisk after its acquisition of Matrix.
As a 25-year industry veteran and IEEE Senior Member, Dr. Fasoli has worked on a variety of non-volatile memory technologies and solid-state storage products, leading product development teams from concept definition to mass production.
Dr. Fasoli has published many technical papers and holds more than 90 U.S. patents.
He earned a doctorate and master’s degree in Electronic Engineering from the Polytechnic University of Milan, and completed the Engineering Leadership Professional Program at UC Berkeley.
He is based at the company’s Milpitas, CA location.
Testing in the 3D NAND Zettabyte era: how to achieve quality and minimize cost
The 3D NAND Flash industry is now approaching the Zettabyte era – an era in which the Flash industry will ship more than a trillion gigabytes every year. Technology innovations in silicon processing, device concepts, circuit design, and system architecture have consistently enabled us to achieve increased performance and reliability over multiple NAND generations.
With every new 3D NAND generation, bit production has increased exponentially while cost per bit has correspondently been decreasing. This trend has disrupted industries and created new markets. From mobile devices and connected vehicles to gaming and data centers, Flash is at the core. Always hidden from view, 3D NAND testing has been evolving to keep up with this on-going revolution. Armies of engineers have been working in parallel to perfect test architectures, test equipment, and test flows to make sure that test cost per bit scales similarly while not affecting product quality.
Transition to the Zettabyte era poses a new set of challenges to the test industry and demands close cooperation between NAND vendors and equipment manufacturers to ensure quality without affecting overall cost per bit. In this keynote, we will cover how Western Digital has been approaching the 3D NAND technology evolution and its testing challenges and relative opportunities.
Tuesday Keynote Speaker
Rebeca Jimenez,
Corporate Vice President Advanced SiP Business Unit, Amkor Technology, Inc.
Rebeca Jimenez joined Amkor in 2014 and is currently Corporate Vice President, Advanced SiP Business Unit. Prior to assuming her current role, Ms. Jimenez served in various sales and strategic program management roles. She has more than 25 years of experience in the global semiconductor industry. Prior to joining Amkor, she spent 15 years with IDT (previously ICS) in both test engineering and operations roles as well as management positions. In addition, Ms Jimenez worked in various engineering and engineering management roles at Motorola. She holds a BS in Electrical Engineering from Arizona State University, as well as an MS in Electrical Engineering from National Technological University.
Advanced Packaging and Test Enabling Our Digital Society
Semiconductors are the building blocks of our modern digital society and allow us to be connected anywhere and everywhere. We interact with semiconductors every day through almost everything we do, whether using our smartphones, personal electronics, connected homes or our cars, which have become digital cockpits, immersed with advanced safety features. All of these digital interactions require massive computing and connectivity power to process, store and transfer data.
Join me as we explore innovations in advanced packaging and test technology and how they enable further transformation in our digital society with a focus on the key catalysts of 5G, High Performance Computing, IoT and Automotive applications.