2002 Southwest Test Workshop
(Each presentation is in Adobe Acrobat format)

TABLE OF CONTENTS

Full Wafer Burn-In Tutorial
Dinner Guest Speakers
Opening Session - Chairman's Welcome
Session 1 - High Power Probing
Session 2 - Process Optimization
Session 3 - Advances in Probe Card Analyzers
Session 4 - Probe Potpourri
Session 5 - C4 Bump Challenges
Session 6 - RF and Parametric Probing
Session 7 - What's Next for Probers?
Session 8 - New Probe Technologies
Session 9 - Probe Process Assessment

Final Test Report - July, 2002 Issue on the SouthWest Test Workshop

"Enabling at Speed Parallel Testing for High Power Products"

Tim Swettlen Abdel Abdelrahman Intel Corp. 2200 Mission College Blvd Santa Clara, CA 95054 408-653-7846 tim.swettlen@intel.com abdel.abdelrahman@intel.com

Winner - Most Inspirational Presentation
"Probing 10 kV and 100 Amps: Challenges and Solutions for High Voltage / High Current Wafer Probing"

Rainer Gaggl, Ph.D. T.I.P.S. Messtechnik GmbH Getreideweg 1, A-9500 Villach +43 4242 319720 r.gaggl@tips.co.at

Session 2 - PROCESS OPTIMIZATION
Top | Session 1 | Session 2 | Session 3 | Session 4 | Session 5 | Session 6 | Session 7 | Session 8 | Session 9

"How to Reach more than 1 Million Touchdowns per Probe Head when Testing High Current / High Pin Count Microprocessors ???"

Jens Kober AMD Saxony Manufacturing GmbH Mail Stop E23-TE Wilschdorfer Landstr. 101 D-01109 Dresden, Germany (+49) 351 - 277 44 13 Jens.Kober@amd.com

"Best Practice Metrology Protocol"

Sal Gullotta Wentworth Laboratories, Inc. 101 Commerce Drive Brookfield, CT 06804 203-775-9311 x 1137 sgullotta@wentworthlabs.com

W. Stuart Crippen Intel Corp. 5000 W. Chandler Blvd. Chandler AZ 85224 480-554-8961 warren.crippen@intel.com

"Extending Probe Card Life for Fine Pitch Probe Cards"

Gene Humphrey International Test Solutions 2479 Chardonnay Way Livermore, CA 94550 925-606-9828 geneh@inttest.net

Session 3 - ADVANCES IN PROBE CARD ANALYZERS
Top | Session 1 | Session 2 | Session 3 | Session 4 | Session 5 | Session 6 | Session 7 | Session 8 | Session 9

"Probe Card Metrology and Correlation at High Temperature"

Rod Schwartz Daniel Kosecki Integrated Technology Corporation 1228 N. Stadem Drive Tempe, Arizona 85281 USA 480-968-3459 rod@inttechcorp.com dank@inttechcorp.com

"Application of Precision Engineering Principles in Linear Stage Design"

Gary Gunderson Applied Precision, LLC 1040 12th Avenue NW Issaquah, WA 98027 425-557-1000 ggunder@api.com

"A Novel, High Precision Approach for Probe Card Metrology"

Raymond Kraft, Ph.D. Applied Precision, LLC 1040 12th Avenue NW Issaquah, WA 98027 425-557-1000 rkraft@api.com

Session 4 - PROBE POTPOURRI
Top | Session 1 | Session 2 | Session 3 | Session 4 | Session 5 | Session 6 | Session 7 | Session 8 | Session 9

"Dynamic Variation of Contact Resistance in Test Interfaces"

Todd Sargent Testdesign / inTest Corporation 1124 Davis St. Redwood City, CA 94061 650-369-5928 wavebox@pacbell.net t.sargent@intest.com

"Advances in Laser Micromachining for Wafer Probing and Trimming"

Andrew Webb Oxford Lasers, Inc. 29 King Street Littleton, MA 01460-1528 800-222-3632 x106 awebb@oxfordlasers.com

"Using MLO Packages to Build Vertical Probe Space Transformers"

Bill Pardee Bill Fulton Wentworth Laboratories, Inc. 101 Commerce Drive Brookfield, CT 06804 203-775-9311 x1189 / x1105 bfulton@wentworthlabs.com bpardee@wentworthlabs.com

Session 5 - C4 BUMP CHALLENGES
Top | Session 1 | Session 2 | Session 3 | Session 4 | Session 5 | Session 6 | Session 7 | Session 8 | Session 9

"Electrical and Mechanical Characterization of MicroSpring BladeRunner tips on Reflowed Eutectic Bumps"

Rod Martens, Ph.D. Form Factor, Inc. 2140 Research Drive Livermore, CA 94550 925-456-3813 rmartens@formfactor.com

Scott Mitchell Texas Instruments, Inc. 13560 North Central Expressway, MS 3738 Dallas TX, 75265 972-995-5055 s-mitchell1@ti.com

Winner - Best Data Presentation
"Probing Lead Free Solder Bumps in Final Wafer Test"

Sam McKnight IBM Microelectronics ZIP 5E1 2070 Route 52 Hopewell Junction, NY 12533 mcknighs@us.ibm.com

"Intel Sort-Interface-Unit (SIU) Design Methods for Reducing Burn Rates on Tight-Pitch C4 Logic Arrays"

Kip Stevenson Pooya Tadayon Intel Corp. Sort Test Technology Development 2501 N.W. 229th Street , RA1-331 Hillsboro, OR 97124 Kip.P.Stevenson@intel.com Pooya.Tadayon@intel.com

Session 6 - RF and PARAMETRIC PROBING
Top | Session 1 | Session 2 | Session 3 | Session 4 | Session 5 | Session 6 | Session 7 | Session 8 | Session 9

"40 GHz on Wafer Testing for Two Port Devices"

Mark Echeagaray MaCom Tech 5300 Hellyer San Jose, CA 408-624-3087 markech@california.com

Winner - Best Presentation, Tutorial in Nature
"RF S-Parameter Measurements - A Production Solution"